1. Field of the Invention
The present invention relates to integrated circuit semiconductor devices, and more specifically, to electrostatic discharge protection devices used in such circuits.
2. Description of the Related Art
Electrostatic discharge (ESD) phenomena commonly result from pulses of high voltage (typically, several kilovolts), moderate current (a few amperes) and short duration (on the order of 100 nanoseconds) generated by a variety of sources such as human bodies, electric fields generated by machinery, and the like. Several analytical models have been developed to approximate these phenomena, including: 1) the Human Body Model (described in more detail in MIL-STD 883C method 3015.7, hereby incorporated by reference), which is typical of ESD resulting from the movement of a human body during, e.g., handling of the device; 2) the Machine Model, which characterizes ESD resulting from charges developed in automated assembly areas; and 3) the Charged Device Model, which approximates ESD from manufacturing and handling devices.
ESD effects are a common problem in integrated circuit (IC) electronics and are particularly troublesome in [complimentary] metal oxide semiconductor (CMOS) devices which have particularly thin gate oxides and very short channel devices. Such structures typically can withstand only a few tens of volts. An ESD pulse conducted through a CMOS IC can induce oxide rupture and device or interconnect burnout, and have potentially disastrous consequences. An ESD pulse can also induce a "latch-up" condition in thick field devices.
ESD problems can be minimized by including appropriate anti-static protection on the circuit boards on which the ICs are installed; however, the ICs still are susceptible to ESD before and during the circuit board fabrication process. A general personnel awareness of ESD problems and countermeasures such as electrically grounded bracelets and the like can abate somewhat risks in this phase of the IC life span; however, it is at best a partial solution. Therefore, it is desirable to include ESD protection circuitry within the IC itself.
One prior art ESD protection circuit involves the use of a resistor interposed between an IC chip bonding pad or terminal and internal IC circuitry. By dropping a portion of the input signal across the resistor, much of the ESD voltage can be dissipated and the CMOS latch-up current can be reduced as well. Unfortunately, the combination of the input resistor and the parasitic capacitance of the bonding pad and input line together generate a significant RC time delay which limits the speed at which the IC operates. Another prior art solution has been to use diodes to shunt the ESD current to ground. This approach has its drawbacks, however, since such diodes typically have a significant parasitic series resistance which limits the amount of current that may be shunted. Furthermore, the forward current increases with temperature due to the increased saturation current and due to the reduced semiconductor band gap. Thus, heating that results from an ESD event further limits current carrying capability. Large area diodes may be used to reduce this resistance; however, this variation reduces the chip density and increases the input circuit's capacitance.
Although the above approaches have proven to be workable, they all operate under the assumption that the circuit being protected is of a single voltage design; that is, all sections of the circuit share a common V.sub.DD. In contrast to single voltage designs, many circuit types make use of a mixed voltage supply scheme, where different sections of the circuit use different operating voltages. An example of this type of circuit is the application specific integrated circuit (ASIC), which may use isolated power and ground busses for I/O and core circuitry, or separate busses for analog and digital circuitry. In ASIC designs which use different power supplies for, e.g., I/O circuitry and core logic, a large amount of power dissipated during an ESD event will cause a small logic area to fail. Conversely, if the logic area is large and the I/O area relatively small, an ESD even may destroy the I/O area instead.